New Computer Processor Has The Potential Of Reaching Trillions Of Calculations Per Second
The prototype for a revolutionary new general-purpose computer
processor, which has the potential of reaching trillions of calculations
per second, has been designed and built by a team of computer
scientists at The University of Texas at Austin.
The new processor, known as TRIPS (Tera-op, Reliable, Intelligently
adaptive Processing System), could be used to accelerate industrial,
consumer and scientific computing. Professors Stephen Keckler, Doug
Burger and Kathryn McKinley have been working on underlying technology
that culminated in the TRIPS prototype for the past seven years. Their
research team designed and built the hardware prototype chips and the
software that runs on the chips.
"The TRIPS prototype is the first on a roadmap that will lead to
ultra-powerful, flexible processors implemented in nanoscale
technologies," said Burger, associate professor of computer sciences.
TRIPS is a demonstration of a new class of processing architectures
called Explicit Data Graph Execution (EDGE). Unlike conventional
architectures that process one instruction at a time, EDGE can process
large blocks of information all at once and more efficiently.
Current "multicore" processing technologies increase speed by adding
more processors, which individually may not be any faster than previous
processors. Adding processors shifts the burden of obtaining better
performance to software programmers, who must assume the difficult task
of rewriting their code to run well on a potentially large number of
processors.
"EDGE technology offers an alternative approach when the race to
multicore runs out of steam," said Keckler, associate professor of
computer sciences. Each TRIPS chip contains two processing cores, each
of which can issue 16 operations per cycle with up to 1,024 instructions
in flight simultaneously. Current high-performance processors are
typically designed to sustain a maximum execution rate of four
operations per cycle.
Though the prototype contains two 16-wide processors per chip, the research team aims to scale this up with further development.
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